
//--Yangxin--

`timescale 1ns / 1ps

`include "defines.v"


module rvcpu(
	input wire clk,
	input wire rst,
	//inst ram interface
	/*output wire        inst_sram_en,
	output wire [7:0]  inst_sram_wen,
	output wire [63:0] inst_sram_addr,
	output wire [63:0] inst_sram_wdata,
	input  wire [63:0] inst_sram_rdata,*/
	output wire [63:0] inst_addr,
	output wire 	   inst_ena,
	input  wire [31:0] inst 
	//data sram interface
	
	/*output wire        data_sram_en,
	output wire [ 7:0] data_sram_wen,
	output wire [63:0] data_sram_addr,
	output wire [63:0] data_sram_wdata,
	input  wire [63:0] data_sram_rdata*/
	);

reg reset;
//always @(posedge clk) reset <= ~resetn;
always @(posedge clk) reset <= rst;


wire        inst_sram_en;
wire [7:0]  inst_sram_wen;
wire [63:0] inst_sram_addr;
wire [63:0] inst_sram_wdata;
wire [31:0] inst_sram_rdata;

assign inst_ena  = inst_sram_en;
assign inst_addr = inst_sram_addr;
assign inst_sram_rdata = inst;

wire        data_sram_en;
wire [ 7:0] data_sram_wen;
wire [63:0] data_sram_addr;
wire [63:0] data_sram_wdata;
wire [63:0] data_sram_rdata;


wire ds_allowin;
wire es_allowin;
wire ms_allowin;
wire ws_allowin;
wire fs_to_ds_valid;
wire ds_to_es_valid;
wire es_to_ms_valid;
wire ms_to_ws_valid;
wire [`FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus;
wire [`DS_TO_ES_BUS_WD -1:0] ds_to_es_bus;
wire [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus;
wire [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus;
wire [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus;
wire [`BR_BUS_WD       -1:0] br_bus      ;
wire [				   69:0] es_to_ds_fwd;
wire [                 68:0] ms_to_ds_fwd;
wire [                 68:0] ws_to_ds_fwd;




//IF stage
if_stage inst_if_stage
    (
	.clk             (clk),
	.reset           (reset),
	//allowin
	.ds_allowin      (ds_allowin),
	//brbus
	.br_bus          (br_bus),
	//outputs
	.fs_to_ds_valid  (fs_to_ds_valid),
	.fs_to_ds_bus    (fs_to_ds_bus),
	//inst sram interfece
	//.inst_addr       (inst_addr),
	.inst_sram_en    (inst_sram_en),
	.inst_sram_wen   (inst_sram_wen),
	.inst_sram_addr  (inst_sram_addr),
	.inst_sram_wdata (inst_sram_wdata),
	.inst_sram_rdata (inst_sram_rdata)
    );

//ID stage
id_stage inst_id_stage
	(
		.clk            (clk),
		.reset          (reset),
		//allowin
		.es_allowin     (es_allowin),
		.ds_allowin     (ds_allowin),
		//from fs
		.fs_to_ds_valid (fs_to_ds_valid),
		.fs_to_ds_bus   (fs_to_ds_bus),
		// to es
		.ds_to_es_valid (ds_to_es_valid),
		.ds_to_es_bus   (ds_to_es_bus),
		//to fs
		.br_bus         (br_bus),
		//forward
		.es_to_ds_fwd   (es_to_ds_fwd),
		.ms_to_ds_fwd   (ms_to_ds_fwd),
		.ws_to_ds_fwd   (ws_to_ds_fwd),
		//to rf:for write back
		.ws_to_rf_bus   (ws_to_rf_bus)
	);

//EXE_stage
exe_stage inst_exe_stage
	(
		.clk             (clk),
		.reset           (reset),
		//allowin
		.ms_allowin      (ms_allowin),
		.es_allowin      (es_allowin),
		//from ds
		.ds_to_es_valid  (ds_to_es_valid),
		.ds_to_es_bus    (ds_to_es_bus),
		//to ms
		.es_to_ms_valid  (es_to_ms_valid),
		.es_to_ms_bus    (es_to_ms_bus),
		//forward
		.es_to_ds_fwd    (es_to_ds_fwd),
		//data sram interface
		.data_sram_en    (data_sram_en),
		.data_sram_wen   (data_sram_wen),
		.data_sram_addr  (data_sram_addr),
		.data_sram_wdata (data_sram_wdata)
	);

//MEM_stage
mem_stage inst_mem_stage
	(
		.clk             (clk),
		.reset           (reset),
		//allowin
		.ws_allowin      (ws_allowin),
		.ms_allowin      (ms_allowin),
		//from es
		.es_to_ms_valid  (es_to_ms_valid),
		.es_to_ms_bus    (es_to_ms_bus),
		//to ws
		.ms_to_ws_valid  (ms_to_ws_valid),
		.ms_to_ws_bus    (ms_to_ws_bus),
		//forward
		.ms_to_ds_fwd    (ms_to_ds_fwd),
		//from data-sram
		.data_sram_rdata (data_sram_rdata)
	);

//WB_stage
wb_stage inst_wb_stage
	(
		.clk            (clk),
		.reset          (reset),
		//allowin
		.ws_allowin     (ws_allowin),
		//from ms
		.ms_to_ws_valid (ms_to_ws_valid),
		.ms_to_ws_bus   (ms_to_ws_bus),
		//to rf
		.ws_to_rf_bus   (ws_to_rf_bus),
		//forward
		.ws_to_ds_fwd   (ws_to_ds_fwd)
	);



endmodule
